SEL-Silvaco unite to develop SPICE model of oxide semiconductor FET

Semiconductor Energy Laboratory Co., Ltd., (SEL) & Silvaco, Inc. have recently announced the joint development of a SPICE model of the oxide semiconductor field effect transistor (FET). This model has been designed for use in various applications, which include the field of AI.

The CAAC-IGZO® FET has an exceptionally low off-leakage current, enabling ultra-low consumption of power of semiconductors such as integrated circuits and memory. It is further expected to serve as a major device in lowering power consumption in the AI era. Moreover, it is a charge-based model with the capability to extend its operation mode and material characteristics. It is also based on the standard model for the multi-gate FinFET, BSIM-CMG, and can reproduce the oxide semiconductor FET’s characteristics.

Several other advantages of the new compact model include:

  • Modeling of interface trapped and sub-gaped localized charges
  • Modeling of L/W scalability & temperature dependence
  • Modeling of the threshold voltage control by the bottom gate
  • Implementation in Verilog-A modeling language
  • Modeling of operation in accumulation mode of the oxide semiconductor

The new model has been generated by Utmost IV, a SPICE model extraction tool of Silvaco, with SEL’s measured data. It has also been verified with SmartSpice, a high-performance circuit simulator of Silvaco. Additionally, it will be adopted by partners that use the CAAC-IGZO® FET technology of SEL.

As per the statement made by SEL’s General Manager of CD Division, Takayuki Ikeda, the CAAC-IGZO® FET technology has a back gate, while the current can be independently controlled of the top gate. The lack of a proper model for the circuit simulation has, however, become a limitation of the design. In order to eliminate this, the company joined hands with Silvaco to form a model for CAAC-IGZO® FET. The company is anticipating the widespread adoption of the new model and technology in the industry.

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